TMPR4938 datasheet(310/716 Pages) TOSHIBA

310 / 716 page

Chapter 10 PCI Controller

10-34

10.4.8 P2G Memory Space 1 PCI Upper Base Address Register (P2GM1PUBASE) 0xD01C

This register is unused since the PCI Controller does not support the target dual-address cycle. It is

forbidden to write to this register.

10.4.9 P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE)

0xD020

This register corresponds to the Memory Space 2 Base Address Register at offset address 0x20 of the

PCI Configuration Space.

This register cannot be accessed when the PCI Controller is in the Satellite mode.

BA[31:20]

Reserved

R/W

: Type

0x000

: Initial value

Reserved

TYPE

MSI

: Type

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:20

BA[31:20]

Base Address

Base Address (Default: 0x00)

Sets the PCI base address in Target Access Memory Space 2. The size of

Memory Space 12 is fixed at 1 MB.

R/W

19:4

Reserved

⎯

Prefetchable

Prefetchable (Fixed Value: 0)

0: Indicates that memory is not prefetchable.

2:1

TYPE

Type

Memory Type (Default: 00)

00: Indicates that an address is within a 32-bit address region.

MSI

Memory Space

Memory Space Indicator (Fixed Value: 0)

0: Indicates that this Base Address Register is for use by the PCI Memory

Space.

Figure 10.4.7 P2G Memory Space 2 PCI Base Address Register

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