ACT72350 datasheet(25/97 Pages) QORVO

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ACT72350 Data Sheet

160V 3 Phase BLDC Motor Driver

Data Sheet v1.1, 2025-02-17

Subject to change without notice

25 of 97

www.qorvo.com

11.5

Linear Regulators

The CPM includes two additional linear regulators, supplied by the VSYS medium voltage regulator. Once

VSYS is above 4.5V, the linear regulators for VCCIO and VCC33 supplies, sequentially power up.

Figure 11-4 Linear Regulators Example

ACT72350

VCC33

VCCIO

VSS

2.2F

The figure above shows typical circuit connections for the linear regulators. The VCCIO regulator

generates a dedicated 3.3V supply for IO. The VCC33 regulator generates 3.3V. When VSYS and the

LDOs above are all above their respective power good thresholds, and the configurable power on reset

duration has expired, the nRESET signal is released from reset state.

11.6

Power-up Sequence

The CPM follows a typical power up sequence as shown in Figure 11-5 below.

Figure 11-5 Power-Up Sequence

VSYS

VCCIO

VCC33

25V

10V

1ms

4. 5V

0. 5

VSYS

VCCIO

VCC33

1ms

15V

3. 3V

nRESET

A typical sequence begins with motor power supply (VM) being applied and rising to 25V. When VM rises

to 25V, the HV-BUCK controller is started and VP starts to rise. When VP rises over the UVLO rising

threshold, then there is a 1ms delay and then the MV-BUCK is enabled. When VSYS rises to 4.5V, then

there is a 0.5ms delay and the VCCIO LDO is enabled. Then there is a 0.5ms delay and the VCC33 LDO

is enabled.

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