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ACT72350 Datasheet(PDF) 36 Page - Qorvo, Inc |
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ACT72350 Datasheet(HTML) 36 Page - Qorvo, Inc |
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36 / 97 page  ACT72350 Data Sheet 160V 3 Phase BLDC Motor Driver Data Sheet v1.1, 2025-02-17 Subject to change without notice 36 of 97 www.qorvo.com ® 11.14.4 SOC.PWRCTL Register 11-4 SOC.PWRCTL (Power Control, 03h) BIT NAME ACCESS RESET DESCRIPTION 7:6 CLKOUTFREQ R/W 0x0 Low-Speed Clock Output Frequency Setting (CLKOUT). 00b: 125kHz 01b: 250kHz 10b: 500KHz 11b: 1 MHz 5 STDBY R/W 0x0 Stand By Mode Enable. This bit is self clearing. 0b: No Stand By Mode (normal LDO operation) ..1b: Enter Stand By Mode (Disables LDO’s) 4 VMSNSEN R/W 0x0 VM Sense Enable. 0b: VM Sense Disabled ..1b: VM Sense Enabled 4:0 WUTIMER R/W 0x0 Wake Up Timer Interval: 0000b = infinite 0001b = 1ms 0010b = 5ms 0011b = 10ms 0100b = 25ms 0101b = 50ms 0110b = 100ms 0111b = 125ms 1000b = 250m 1001b = 500ms 1010b = 750ms 1011b = 1s 1100b = 2s 1101b = 4s 1110b = 6s 1111b = 8s |
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