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ACT72350 Datasheet(PDF) 38 Page - Qorvo, Inc |
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ACT72350 Datasheet(HTML) 38 Page - Qorvo, Inc |
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38 / 97 page  ACT72350 Data Sheet 160V 3 Phase BLDC Motor Driver Data Sheet v1.1, 2025-02-17 Subject to change without notice 38 of 97 www.qorvo.com ® 11.14.6 SOC.WATCHDOG Register 11-6 SOC.WATCHDOG (SOC Watchdog Configuration, 05h) BIT NAME ACCESS RESET DESCRIPTION 7 SRST R/W 0x0 Soft Reset. This bit can be set to issue a system soft reset. This bit is always read as 0b. When set, the STATUS.SRST bit will be latched to a 1b so the MCU knows the system is being started after a soft reset. 0b: Do not issue soft reset 1b: Issue soft reset 6:4 RFU R 0x0 Reserved, write as 0. 3 WDTEN R/W 0x0 Watchdog Timer Enable. Cleared during hard reset. 0b: disabled 1b: enabled 2:0 TWD R/W 0x0 Watch-dog Timer. 000b: 62.5ms 001b: 125ms 010b: 250ms 011b: 500ms 100b: 1s 101b: 2s 110b: 4s 111b: 8s |
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