ACT72350 datasheet(42/97 Pages) QORVO

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ACT72350 Data Sheet

160V 3 Phase BLDC Motor Driver

Data Sheet v1.1, 2025-02-17

Subject to change without notice

42 of 97

www.qorvo.com

12.3

Introduction

The device includes a Configurable Analog Front End (CAFE, Figure 12-1) accessible through 10 analog

input and 7 analog output pins. These pins can be configured to form flexible interconnected circuitry

made up of 3 differential programmable gain amplifiers, 4 single-ended programmable gain amplifiers, 4

general purpose comparators, 3 phase comparators, and one buffer output. A push button function is

provided for optional push button on Hibernate and Stand By modes.

12.4

Differential Programmable Gain Amplifier (DA)

The DAxP and DAxN pin pair are positive and negative inputs, respectively, to a differential

programmable gain amplifier. The differential gain can be programmable to be 1x, 2x, 4x, 8x, 16x, 32x,

and 48x for zero ohm signal source impedance. The differential programmable gain amplifier has -0.3V to

2.5V input common mode range, and its output can be configured for routing directly as a live analog

output, or through a sample-and-hold circuit synchronized with the external ADC sampling engine. Each

differential amplifier is accompanied by offset calibration circuitry, and two protection comparators for

protection event monitoring. The programmable gain differential amplifier is optimized for use with signal

source impedance lower than 500Ω and with matched source impedance on both positive and negative

inputs for minimal offset. The effective gain is scaled by 13.5k / (13.5k + RSOURCE), where RSOURCE is the

matched source impedance of each input.

12.5

Single-Ended Programmable Gain Amplifier (AMP)

Each AMPx input goes to a single-ended programmable gain amplifier with signal relative to VSS. The

amplifier gain can be programmed to be 1x, 2x, 4x, 8x, 16x, 32x, and 48x, or as analog feed-through. The

programmable gain amplifier output is routed into its independent output for easy access into the

application’s microcontroller analog inputs.

12.6

General Purpose Comparator (CMP)

The general purpose comparator takes the CMPx input and compares it to the programmable threshold

voltage (VTHREF). The comparator has 0V to VSYS input common mode range, and its polarity-selectable

output is routed into its respective output.

12.7

Phase Comparator (PHC)

The phase comparator takes the PHCx input and compares it to either the programmable threshold

voltage (VTHREF) or a phase reference signal generated by averaging the PHCx input voltages. In a three-

phase motor control application, the phase reference signal acts as a virtual center tap for BEMF

detection. The PHC inputs can be compared to the virtual center-tap, or phase to phase for the most

efficient BEMF zero-cross detection.

The phase comparator signals can also be configured to the other two phase comparators (between

AIO7, AIO8 and AIO9), to perform phase to phase comparisons.

The comparator blanking time is configurable. The blanking time configuration supports bi-directional and

asymmetric configurations, which enables hysteresis for rising and falling signals.

The phase comparator has 0V to VSYS input common mode range, and its polarity-selectable output is

routed to a data input bit and to the phase/position multiplexer synchronized with the auto-sampling

sequencers.

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