27
0832F–HIREL–02/07
e2v semiconductors SAS 2007
PC7410
Note:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L2SYNC_IN (see Figure 9-6). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the sig-
nal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50
Ω load (see
Figure 9-8 on page 28).
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous burst
RAMs, L2CR[14:15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14:15] = 10 is
recommended.
Figure 9-6.
L2 Bus Input Timing Diagram
Note:
VM = Midpoint Voltage (L2OVDD/2)
tL2CHOV
(3)(4)
Valid Times
All outputs when L2CR[14:15] = 00
All outputs when L2CR[14:15] = 01
All outputs when L2CR[14:15] = 10
All outputs when L2CR[14:15] = 11
2.5
2.5
2.9
3.5
ns
tL2CHOX
(3)
Output Hold Times
All outputs when L2CR[14:15] = 00
All outputs when L2CR[14:15] = 01
All outputs when L2CR[14:15] = 10
All outputs when L2CR[14:15] = 11
0.4
0.8
1.2
1.6
ns
tL2CHOZ
L2SYNC_IN to high impedance
All outputs when L2CR[14:15] = 00
All outputs when L2CR[14:15] = 01
All outputs when L2CR[14:15] = 10
All outputs when L2CR[14:15] = 11
2.0
2.5
3.0
3.5
ns
Table 9-5.
L2 Bus Interface AC Timing Specifications at V
DD = AVDD = L2AVDD = 1.8V ± 100mV or 1.5V ± 50mV ;
-55°C
≤T
J ≤125°C, L2OVDD = 2.5V ± 100mV or L2OVDD = 1.8V ± 100mV (Continued)
Symbol
Parameter
400, 450, 500 MHz
Unit
Min
Max
L2SYNC_IN
L2 Data and Data
Parity Inputs
tL2CR
tL2CF
tDVL2CH
tDXL2CH
VM
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
