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0832F–HIREL–02/07
e2v semiconductors SAS 2007
PC7410
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of
the signal in question. The output timings are measured at the pins. All output timings assume a purely
resistive 50
Ω load (see Figure 9-9). Time-of-flight delays must be added for trace lengths, vias and con-
nectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Figure 9-9.
Alternate AC Test Load for the JTAG Interface
Figure 9-10. JTAG Clock Input Timing Diagram
Note:
VM = Midpoint Voltage (OV
DD/2)
Figure 9-11. TRST Timing Diagram
Note:
VM = Midpoint Voltage (OV
DD/2)
Z0 = 50
Ω
RL = 50
Ω
OVDD/2
Output
TCLK
tJR
tJF
tJHJL
tTCLK
VM
VM
VM
TRST
tTRST
VM
VM
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