3 / 57 page
Fetcher
Branch Processing Unit
Instruction
Queue
6-word
Dispatch Unit
Instruction Unit
Data MMU
SRs
(Original)
128-entry
DTLB
DBAT
Array
Instruction MMU
SRs
(Shadow)
128-entry
ITLB
IBAT
Array
Reservation
Station
Vector
Permute
Unit
Vector
ALU
Integer
Unit 1
Integer
Unit 2
System
Register
Unit
Reservation
Station
Reservation
Station
Reservation
Station
Reservation
Station
Reservation
Station
2-entry
Reservation
Station
VR File
6 Rename
Buffers
GPR File
6 Rename
Buffers
FPR File
6 Rename
Buffers
Load/Store
Unit
Floating
Point Unit
Completion Unit
8-entry
Reorder Buffer
VSIU VCIU VFPU
Tags
32-Kbyte
iCache
Tags
32-Kbyte
DCache
64-entry BTIC/512-entry BHT
LR/CTR
Add-Multiply-
divide
- Add -
VSCR
- Add -
Add-Multiply-
divide
FPSCR
EA Calculation
Finished Stores
Completed
Stores
128-bit
32-bit
128-bit
2 Instructions
32-bit
64-bit
(2 Instructions)
32-bit Address Bus
64- or 32-bit L2 Data Bus
19-bit L2 Address Bus
64-bit Data Bus
32-bit
EA
PA
64-bit
64-bit
Data Reload
Buffer
Data Reload
Table
Instruction
Reload Buffer
Instruction
Reload Table
Memory Subsystem
L2 Miss
Data
Transaction
Queue
L2 Castout
Bus Interface Unit
L2 Data
Transaction
Queue
L2 Controller
L2 Tags
L2CR
L2PMCR
Additional features
Time Base
Counter/Decrementer
Clock Multiplier
JTAG/COP Interface
Thermal/Power Management
Performance Monitor
128 bits
128 bits
(4 instructions)
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
