PC7410 datasheet(36/57 Pages) ETC2

36 / 57 page

0832F–HIREL–02/07

PC7410

e2v semiconductors SAS 2007

3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVDD

(selects 2.5V), GND (selects 1.8V), or to HRESET (selects 2.5V). The PC7410 Both the 60x processor bus and the L2 bus

only support the 1.8 and 2.5 options (see Table 6-2 on page 10). the default selection if BVSEL and/or L2VSEL is left uncon-

nected is 2.5V.

4. Connect to HRESET to trigger post power-on-reset (por) internal memory test.

5. Ignored in 60x bus mode.

6. Unused output in 60x bus mode.

7. Deasserted (pulled high) at HRESET for 60x bus mode.

8. Uses one of 9 existing no-connects in PC750’s 360-ball BGA package.

9. Internal pull-up on die.

10. Reuses PC750’s DRTRY, DBDIS and TLBISYNC pins (DTI1, DTI2 and EMODE respectively).

11. The VOLTDET pin position on the PC750 360-ball CBGA package is now an L2OVDD pin on the PC7410 packages.

12. Output only for PC7410, was I/O for PC750.

13. Enhanced mode only.

14. To overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down resistance less

than 250

Ω should be used.

PC7410 Datasheet(PDF) 36 Page - List of Unclassifed Manufacturers