CP321
Functional Description
ID 24977, Rev. 02
© 2003 Kontron Modular Computers GmbH
Page 2 - 3
2.
Functional Description
The following chapters provide more detailed board information covering the following: board
general information, memory, board interfaces, special functions, and options.
2.1
General Information
The CP321 is based on the Motorola PowerPC processor MPC8245 which integrates a large
number of peripherals, such as a FPU PCI interface, PCI arbiter, Interrupt Controller, Memory
and DMA Controller and multiple Timers.
Important features of the CP321 are as follows:
603e Core:
•
CPU speed is 330 MHz.
•
high performance, superscalar 603e core
•
627 Dhrystone (2.1) MIPS
•
integer unit (IU), floating point unit (FPU) (user enabled or disabled), load/store unit
(LSU), system register unit (SRU), and a branch processing unit (BPU)
•
16 kB instruction cache
•
16 kB data cache
•
lockable L1 cache - entire cache or on a per-way basis
•
dynamic power management
•
I²C controller with full master/slave support
Memory Interface:
•
programmable timing support for SDRAM
(The CP321 uses SDRAM at 132 MHz)
•
high bandwidth bus (64-bit data bus) to SDRAM
•
2 memory banks with up to 128 MB each (64, 128 or 256 Mbit memory devices)
•
supports 32, 64, 128 and 256 MB SDRAM
•
contiguous memory mapping
•
8-bit ROM interface
•
write buffering for PCI and processor accesses
•
supports ECC
•
SDRAM data path buffer
•
low voltage transistor-to-transistor logic (LVTTL)
•
Port X: 8-bit general-purpose I/O port using ROM controller
interface with address strobe
32-bit PCI Interface:
•
operates up to 33 MHz
•
PCI Specification Revision 2.1 compatible
•
universal board (3.3V or 5V signaling on CPCI)
•
support for PCI-locked accesses to memory
•
support for accesses to all PCI address spaces
•
selectable big or little-endian operation (default on the CP321 is big-endian)
•
store gathering of processor-to-PCI write and PCI-to-memory write accesses
•
memory prefetching of PCI read accesses
•
selectable hardware-enforced coherency
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