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F24 Datasheet(PDF) 128 Page - Renesas Technology Corp |
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F24 Datasheet(HTML) 128 Page - Renesas Technology Corp |
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128 / 210 page  RL78/F23, F24 4. ELECTRICAL SPECIFICATIONS (GRADE 4) R01DS0446EJ0120 Rev.1.20 Page 128 of 207 Dec 31, 2025 UART mode bit width (during communication at different potential) (reference) Caution Select the TTL input buffer for the RXD0 pin and RXD1 pin and N-ch open-drain output mode for the TXD0 pin and TXD1 pin. Remarks 1. Rb [Ω]: Communication line (TXD) pull-up resistance, Cb [F]: Communication line (TXD) load capacitance, Vb [V]: Communication line voltage 2. fMCK: Serial array unit operation clock frequency TXD0, TXD1 RXD0, RXD1 Baud rate error tolerance 1/Transfer rate High-/low-bit width Baud rate error tolerance 1/Transfer rate High-bit width Low-bit width |
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