F24 datasheet(131/210 Pages) RENESAS

131 / 210 page

RL78/F23, F24

4. ELECTRICAL SPECIFICATIONS (GRADE 4)

R01DS0446EJ0120 Rev.1.20

Page 131 of 207

Dec 31, 2025

(10) During communication at different potential (3-V supply system) (CSI mode) (slave mode, SCKp … external

clock input, normal slew rate)

(TA = -40 to +125

°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCKp cycle time

tKCY2

2.7 V

≤ Vb ≤ VDD

32 MHz < fMCK

20/fMCK

24 MHz < fMCK

≤ 32 MHz

16/fMCK

20 MHz < fMCK

≤ 24 MHz

12/fMCK

8 MHz < fMCK

≤ 20 MHz

10/fMCK

4 MHz < fMCK

≤ 8 MHz

8/fMCK

fMCK

≤ 4 MHz

6/fMCK

SCKp high-level width,

low-level width

tKH2, tKL2

2.7 V

≤ Vb ≤ VDD

tKCY2/2 – 20

SIp setup time

(to SCKp

↑) Note 1

tSIK2

SIp hold time

(from SCKp

↑) Note 2

tKSI2

1/fMCK + 50

Delay time from SCKp

↓ to

SOp output Note 3

tKSO2

2.7 V

≤ Vb ≤ VDD, Cb = 30 pF, Rb = 1.4 kΩ

2/fMCK + 120

SSIp setup time

tSSIK

DAP = 0

120

DAP = 1

1/fMCK + 120

SSIp hold time

tKSSI

DAP = 0

1/fMCK + 120

DAP = 1

120

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The Slp setup time becomes “to SCKp

↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0.

2. When DAPmn = 0 and CKPmn = 0 or DAPmn = 1 and CKPmn = 1.

The SIp hold time becomes “from SCKp

↓” when DAPmn = 0 and CKPmn = 1 or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The delay time to SOp output becomes “from SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and

CKPmn = 0.

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