F24 datasheet(129/210 Pages) RENESAS

129 / 210 page

RL78/F23, F24

4. ELECTRICAL SPECIFICATIONS (GRADE 4)

R01DS0446EJ0120 Rev.1.20

Page 129 of 207

Dec 31, 2025

(9)

During communication at different potential (3-V supply system) (CSI mode) (master mode, SCKp … internal

clock output, normal slew rate)

(TA = -40 to +125

°C, 4.0 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCKp cycle time

tKCY1

2.7 V

≤ Vb ≤ EVDD0,

Cb = 30 pF, Rb = 1.4 kΩ

400 Note 3

SCKp high-level width

tKH1

2.7 V

≤ Vb ≤ EVDD0,

Cb = 30 pF, Rb = 1.4 kΩ

tKCY1/2 – 75

SCKp low-level width

tKL1

2.7 V

≤ Vb ≤ EVDD0,

Cb = 30 pF, Rb = 1.4 kΩ

tKCY1/2 – 20

SIp setup time (to SCKp

↑) Note 1

tSIK1

2.7 V

≤ Vb ≤ EVDD0,

Cb = 30 pF, Rb = 1.4 kΩ

150

SIp setup time (to SCKp

↓) Note 2

tSIK1

2.7 V

≤ Vb ≤ EVDD0,

Cb = 30 pF, Rb = 1.4 kΩ

SIp hold time (from SCKp

↑) Note 1

tKSI1

2.7 V

≤ Vb ≤ EVDD0,

Cb = 30 pF, Rb = 1.4 kΩ

SIp hold time (from SCKp

↓) Note 2

tKSI1

2.7 V

≤ Vb ≤ EVDD0,

Cb = 30 pF, Rb = 1.4 kΩ

Delay time from SCKp

↓ to SOp output Note 1

tKSO1

2.7 V

≤ Vb ≤ EVDD0,

Cb = 30 pF, Rb = 1.4 kΩ

120

Delay time from SCKp

↑ to SOp output Note 2

tKSO1

2.7 V

≤ Vb ≤ EVDD0,

Cb = 30 pF, Rb = 1.4 kΩ

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. tKCY1

≥ 4/fMCK must also be satisfied.

CSI mode connection diagram (during communication at different potential)

Caution Select the TTL input buffer for the SIp pin and N-ch open-drain output mode for the SOp pin and

SCKp pin.

Remarks 1. Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SOp, SCKp) load

capacitance, Vb [V]: Communication line voltage

2. p: CSIp (p = 00, 01, 10, 11), m: Unit m (m = 0, 1), n: Channel n (n = 0, 1)

3. AC characteristics of the serial array unit during communication at different potential in CSI mode are

measured with the VIH and VIL below:

When 4.0 V

≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V

User's device

RL78

microcontroller

SCKp

SSIp

SCK

SOp

SIp

<R>

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