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LAN9313 Datasheet(PDF) 36 Page - SMSC Corporation |
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LAN9313 Datasheet(HTML) 36 Page - SMSC Corporation |
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36 / 398 page ![]() Three Port 10/100 Managed Ethernet Switch with MII Datasheet Revision 1.2 (04-08-08) 36 SMSC LAN9313/LAN9313i DATASHEET Note: For more information on configuration straps, refer to Section 4.2.4, "Configuration Straps," on page 45. Additional strap pins, which share functionality with the EEPROM pins, are described in Table 3.6. Note 3.8 This signal is pulled high through an internal pull-up resistor at all times. 30 Port 0 (External MII) Full-Duplex Flow Control Enable Strap FD_FC_MII IS (PU) Note 3.8 Port 0(External MII) Full-Duplex Flow Control Enable Strap: Configures the default of the TX_FC_MII and RX_FC_MII bits in the Port 0(External MII) Manual Flow Control Register (MANUAL_FC_MII). When latched low, flow control is disabled on RX/TX. When latched high, flow control is enabled on RX/TX. See Note 3.9. 29 Port 0 (External MII) Manual Flow Control Enable Strap MANUAL_FC_MII IS (PU) Note 3.8 Port 0(External MII) Manual Flow Control Enable Strap: Configures the default value of the MANUAL_FC_MII bit in the Port 0(External MII) Manual Flow Control Register (MANUAL_FC_MII). When latched low, flow control is determined by Virtual Auto-Negotiation. When latched high, flow control is determined by TX_FC_MII and RX_FC_MII bits in the Port 0(External MII) Manual Flow Control Register (MANUAL_FC_MII). See Note 3.9, and Note 3.10. 26,28 Serial Management Mode Strap MNGT_MODE[1:0] IS (PU) Note 3.8 Serial Management Mode Strap: Configures the serial management mode. 00 = Unmanaged mode 01 = SMI Managed Mode 10 = I2C Managed Mode 11 = SPI Managed Mode See Note 3.9. 25 MII Mode Strap MII_MODE IS (PU) Note 3.8 MII Mode Strap: Configures the mode of the external MII port. 0 = MAC Mode 1 = PHY Mode See Note 3.9. 95 PHY Address Strap PHY_ADDR_SEL IS (PU) Note 3.8 PHY Address Strap: Configures the default MII management address values for the PHYs (Virtual, Port 1, and Port 2) as detailed in Section 7.1.1, "PHY Addressing," on page 84. See Note 3.9. Table 3.5 Dedicated Configuration Strap Pins (continued) PIN NAME SYMBOL BUFFER TYPE DESCRIPTION 0 01 2 1 12 3 |
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