LAN9313 datasheet(46/398 Pages) SMSC

46 / 398 page

Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

Revision 1.2 (04-08-08)

SMSC LAN9313/LAN9313i

DATASHEET

auto_mdix_strap_1

Port 1 Auto-MDIX Enable Strap: Configures the default

value for the Auto-MDIX functionality on Port 1 when the

AMDIXCTL bit in the Port x PHY Special Control/Status

Indication Register

(PHY_SPECIAL_CONTROL_STAT_IND_x) is cleared.

When configured low, Auto-MDIX is disabled. When

configured high, Auto-MDIX is enabled.

Note:

If AMDIXCTL is set, this strap had no effect.

AUTO_MDIX_1

manual_mdix_strap_1

Port 1 Manual MDIX Strap: Configures MDI(0) or MDIX(1)

for Port 1 when the auto_mdix_strap_1 is low and the

AMDIXCTL bit of the Port x PHY Special Control/Status

Indication Register

(PHY_SPECIAL_CONTROL_STAT_IND_x) is cleared.

autoneg_strap_1

Port 1 Auto Negotiation Enable Strap: Configures the

default value for the Auto-Negotiation (PHY_AN) enable bit

in the PHY_BASIC_CTRL_1 register (See

Section 13.2.2.1). When configured low, auto-negotiation is

disabled. When configured high, auto-negotiation is

enabled.

This strap also affects the default value of the following bits:

PHY_SPEED_SEL_LSB and PHY_DUPLEX bits of the

Port x PHY Basic Control Register

(PHY_BASIC_CONTROL_x)

10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex

(bit 5) bits of the Port x PHY Auto-Negotiation

Advertisement Register (PHY_AN_ADV_x)

MODE[2:0] bits of the Port x PHY Special Modes Register

(PHY_SPECIAL_MODES_x)

Refer to the respective register definition sections for

additional information.

AUTO_NEG_1

speed_strap_1

Port 1 Speed Select Strap: Configures the default value

for the Speed Select LSB (PHY_SPEED_SEL_LSB) bit in

the PHY_BASIC_CTRL_1 register (See Section 13.2.2.1).

When configured low, 10 Mbps is selected. When

configured high, 100 Mbps is selected.

This strap also affects the default value of the following bits:

PHY_SPEED_SEL_LSB bit of the Port x PHY Basic

Control Register (PHY_BASIC_CONTROL_x)

10BASE-T Full Duplex (bit 6) and 10BASE-T Half Duplex

(bit 5) bits of the Port x PHY Auto-Negotiation

Advertisement Register (PHY_AN_ADV_x)

MODE[2:0] bits of the Port x PHY Special Modes Register

(PHY_SPECIAL_MODES_x)

Refer to the respective register definition sections for

additional information.

SPEED_1

Table 4.2 Soft-Strap Configuration Strap Definitions (continued)

STRAP NAME

DESCRIPTION

PIN / DEFAULT

VALUE

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