LAN9313 datasheet(78/398 Pages) SMSC

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Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

Revision 1.2 (04-08-08)

SMSC LAN9313/LAN9313i

DATASHEET

Note: When specifying Port 0 as the destination port, the VID will be set to 0. A VID of 0 is normally

considered a priority tagged packet. Such a packet will be filtered if Admit Only VLAN is set

on the host CPU port. Either avoid setting Admit Only VLAN on the host CPU port or set an

unused bit in the VID field.

Note: The maximum size tagged packet that can normally be sent into a switch port (from the MII

port) is 1522 bytes. Since the special tag consumes four bytes of the packet length, the

outgoing packet is limited to 1518 bytes, even if it contains a regular VLAN tag as part of the

packet data. If a larger outgoing packet is required, the Jumbo2K bit in the Port x MAC Receive

Configuration Register (MAC_RX_CFG_x) of Port 0 should be set.

6.4.10.2

Packets to the Host CPU

The Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) configures the switch to

add the special VLAN tag in packets to the host CPU as a source port indicator. A setting of 11b should

be used only on the port that is connected to the host CPU (typically Port 0). Other settings can be

used on the normal network ports as needed.

The special VLAN tag is a normal VLAN tag where bits 0 and 1 of the VID field specify the source

port (0, 1, or 2).

Upon egress from the host CPU port, the special tag is added. If a regular VLAN tag already exists,

it is not deleted. Instead it will follow the special tag.

6.4.11

Counters

A counter is maintained per port that contains the number of MAC address that were not learned or

were overwritten by a different address due to MAC Address Table space limitations. These counters

are accessible via the following registers:

Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII)

Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1)

Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2)

A counter is maintained per port that contains the number of packets filtered at ingress. This count

includes packets filtered due to broadcast throttling, but does not include packets dropped due to

ingress rate limiting. These counters are accessible via the following registers:

Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII)

Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1)

Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2)

6.5

Buffer Manager (BM)

The buffer manager (BM) provides control of the free buffer space, the multiple priority transmit

queues, transmission scheduling, and packet dropping. VLAN tag insertion and removal is also

performed by the buffer manager. The following sections detail the various features of the buffer

manager.

6.5.1

Packet Buffer Allocation

The packet buffer consists of 32KB of RAM that is dynamically allocated in 128 byte blocks as packets

are received. Up to 16 blocks may be used per packet, depending on the packet length. The blocks

are linked together as the packet is received. If a packet is filtered, dropped, or contains a receive

error, the buffers are reclaimed.

LAN9313 Datasheet(PDF) 78 Page - SMSC Corporation

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