LAN9313 datasheet(39/398 Pages) SMSC

39 / 398 page

Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

Revision 1.2 (04-08-08)

DATASHEET

Note 3.14 The input buffers are enabled when configured as GPIO inputs only.

Table 3.8 Miscellaneous Pins

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

77-79,

General

Purpose I/O

Data

GPIO[11:8]

IS/OD12/

O12

(PU)

Note 3.14

General Purpose I/O Data: These general

purpose signals are fully programmable as either

push-pull outputs, open-drain outputs, or Schmitt-

triggered inputs by writing the General Purpose I/O

Configuration Register (GPIO_CFG) and General

Purpose I/O Data & Direction Register

(GPIO_DATA_DIR). For more information, refer to

Chapter 12, "GPIO/LED Controller," on page 142.

Note:

The remaining GPIO[7:0] pins share

functionality with the LED output pins, as

described in Table 3.1 and Table 3.2.

Interrupt

Output

IRQ

O8/OD8

Interrupt Output: Interrupt request output. The

polarity, source and buffer type of this signal is

programmable via the Interrupt Configuration

Chapter 5, "System Interrupts," on page 52.

System Reset

Input

nRST

(PU)

System Reset Input: This active low signal allows

external hardware to reset the LAN9313/LAN9313i.

The LAN9313/LAN9313i also contains an internal

power-on reset circuit. Thus, this signal may be left

unconnected if an external hardware reset is not

needed. When used, this signal must adhere to the

reset timing requirements as detailed in Section

14.5.2, "Reset and Configuration Strap Timing," on

page 390.

Test 1

TEST1

Test 1: This pin must be tied to VDD33IO for

proper operation.

108

Test 2

TEST2

Test 2: This pin must be tied to VDD33IO for

proper operation.

Table 3.9 PLL Pins

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

107

PLL +1.8V

Power Supply

VDD18PLL

PLL +1.8V Power Supply: This pin must be

connected to VDD18CORE for proper operation.

Refer to the LAN9313/LAN9313i application note

for additional connection information.

105

Crystal Input

ICLK

Crystal Input: External 25MHz crystal input. This

signal can also be driven by a single-ended clock

oscillator. When this method is used, XO should be

left unconnected.

106

Crystal

Output

OCLK

Crystal Output: External 25MHz crystal output.

LAN9313 Datasheet(PDF) 39 Page - SMSC Corporation

LAN9313 Datasheet(HTML) 39 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL