LAN9313 datasheet(51/398 Pages) SMSC

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Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

Revision 1.2 (04-08-08)

DATASHEET

4.3

Power Management

The LAN9313/LAN9313i Port 1 and Port 2 PHYs support several power management and wakeup

features.

4.3.1

Port 1 & 2 PHY Power Management

The Port 1 & 2 PHYs provide independent general power-down and energy-detect power-down modes

which reduce PHY power consumption. General power-down mode provides power savings by

powering down the entire PHY, except the PHY management control interface. General power-down

mode must be manually enabled and disabled as described in Section 7.2.9.1, "PHY General Power-

Down," on page 97.

In energy-detect power-down mode, the PHY will resume from power-down when energy is seen on

the cable (typically from link pulses). If the ENERGYON interrupt (INT7) of either PHYs Port x PHY

Interrupt Mask Register (PHY_INTERRUPT_MASK_x) is unmasked, then the corresponding PHY will

generate an interrupt. These interrupts are reflected in the Interrupt Status Register (INT_STS) bit 27

(PHY_INT2) for the Port 2 PHY, and bit 26 (PHY_INT1) for the Port 1 PHY. These interrupts can be

used to trigger the IRQ interrupt output pin, as described in Section 5.2.3, "Ethernet PHY Interrupts,"

on page 55. Refer to Section 7.2.9.2, "PHY Energy Detect Power-Down," on page 97 for details on the

operation and configuration of the PHY energy-detect power-down mode.

eeprom_size_strap[1:0]

EEPROM Size Strap [1:0]: Configures the EEPROM size

range as specified in Section 8.2, "I2C/Microwire Master

EEPROM Controller," on page 101.

EEPROM_SIZE_[1:0]

MII_mode_strap

MII Mode Strap: Configures the default mode of the

external MII port.

0 = MAC Mode

1 = PHY Mode

Refer to Section 2.3, "Modes of Operation," on page 23 for

additional information on the various modes of the

LAN9313/LAN9313i.

MII_MODE

phy_addr_sel_strap

PHY Address Select Strap: Configures the default MII

management address values for the PHYs and Virtual PHY

as detailed in Section 7.1.1, "PHY Addressing," on page 84.

PHY_ADDR_SEL

Table 4.3 Hard-Strap Configuration Strap Definitions

STRAP NAME

DESCRIPTION

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