C167CS datasheet(331/517 Pages) INFINEON

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C167CS

Derivatives

The Capture/Compare Units

User’s Manual

16-13

V2.0, 2000-07

16.4

Capture Mode

In response to an external event the content of the associated timer (T0/T1 or T7/T8,

depending on the used CAPCOM unit and the state of the allocation control bit ACCx) is

latched into the respective capture register CCx. The external event causing a capture

can be programmed to be either a positive, a negative, or both a positive or a negative

transition at the respective external input pin CCxIO.

The triggering transition is selected by the mode bits CCMODx in the respective

CAPCOM mode control register. In any case, the event causing a capture will also set

the respective interrupt request flag CCxIR, which can cause an interrupt or a PEC

service request, when enabled.

Figure 16-5

Capture Mode Block Diagram

In order to use the respective port pin as external capture input pin CCxIO for capture

control bit must be set to ‘0’. To ensure that a signal transition is properly recognized, an

external capture input signal should be held for at least 8 CPU clock cycles before it

changes its level.

During these 8 CPU clock cycles the capture input signals are scanned sequentially.

When a timer is modified or incremented during this process, the new timer contents will

already be captured for the remaining capture registers within the current scanning

sequence.

Note: When the timer modification can generate an overflow the capture interrupt

routine should check if the timer overflow was serviced during these 8 CPU clock

cycles.

If pin CCxIO is configured as output, the capture function may be triggered by modifying

the corresponding port output latch via software, e.g. for testing purposes.

Edge

Select

MCB02015

Capture Reg. CCx

CAPCOM Timer Ty

Interrupt

Request

CCxIO

Input

Clock

CCMODx

Interrupt

Request

x = 31...0

y = 0, 1, 7, 8

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