C167CS datasheet(332/517 Pages) INFINEON

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C167CS

Derivatives

The Capture/Compare Units

User’s Manual

16-14

V2.0, 2000-07

16.5

Compare Modes

The compare modes allow triggering of events (interrupts and/or output signal

transitions) with minimum software overhead. In all compare modes, the 16-bit value

stored in compare register CCx (in the following also referred to as ‘compare value’) is

continuously compared with the contents of the allocated timer (T0/T1 or T7/T8). If the

current timer contents match the compare value, an appropriate output signal, which is

based on the selected compare mode, can be generated at the corresponding output pin

CCxIO and the associated interrupt request flag CCxIR is set, which can generate an

interrupt request (if enabled).

As for capture mode, the compare registers are also processed sequentially during

compare mode. When two or more compare registers are programmed to the same

compare value, their corresponding interrupt request flags will be set to ‘1’ and the

selected output signals will be generated within 8 CPU clock cycles after the allocated

timer is incremented to this compare value. Further compare events on the same

compare value are disabled1) until the timer is incremented again or written to by

software. After a reset, compare events for register CCx will only become enabled, if the

allocated timer has been incremented or written to by software and one of the compare

modes described in the following has been selected for this register.

The different compare modes which can be programmed for a given compare register

CCx are selected by the mode control field CCMODx in the associated capture/compare

mode control register. In the following, each of the compare modes, including the special

‘double-register’ mode, is discussed in detail.

Compare Mode 0

This is an interrupt-only mode which can be used for software timing purposes. Compare

mode 0 is selected for a given compare register CCx by setting bit field CCMODx of the

corresponding mode control register to ‘100B’.

In this mode, the interrupt request flag CCxIR is set each time a match is detected

between the content of compare register CCx and the allocated timer. Several of these

compare events are possible within a single timer period, when the compare value in

affected by compare events in this mode and can be used as general purpose IO pin.

If compare mode 0 is programmed for one of the registers CC8 … CC15 or

CC24 … CC31, the double-register compare mode becomes enabled for this register if

the corresponding bank 1 register is programmed to compare mode 1 (see “Double-

1) Compare events are detected sequentially, where a sequence (checking 8 times 2 channels each) takes

8 CPU clock cycles. Even if more sequences are executed before the timer increments (lower timer frequency)

a given compare value only results in one single compare event.

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