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38D2 Datasheet(PDF) 102 Page - Renesas Technology Corp |
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38D2 Datasheet(HTML) 102 Page - Renesas Technology Corp |
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102 / 136 page  Rev.3.02 Apr 10, 2008 Page 102 of 131 REJ03B0177-0302 38D2 Group Timing Requirements and Switching Characteristics NOTES: 1. 80 ns in the frequency/2 mode. 2. 32 ns in the frequency/2 mode. 3. When bit 6 of address 001A16, 001F16 are “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16, 001F16 are “0” (UART). NOTE: 1. When bit 6 of address 001A16, 001F16 are “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16, 001F are “0” (UART). Table 30 Timing requirements (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = −20 to 85°C, unless otherwise noted) Symbol Parameter Limits Unit Min. Typ. Max. tW(RESET) Reset input “L” pulse width 2 μs tC(XIN) Main clock input cycle time 4.5V ≤ VCC ≤ 5.5V (1) 62.5 ns 4.0V ≤ VCC < 4.5V 125 ns tWH(XIN) Main clock input “H” pulse width 4.5V ≤ VCC ≤ 5.5V (2) 25 ns 4.0V ≤ VCC < 4.5V 50 ns tWL(XIN) Main clock input “L” pulse width 4.5V ≤ VCC ≤ 5.5V (2) 25 ns 4.0V ≤ VCC < 4.5V 50 ns tC(CNTR) CNTR0, CNTR1 input cycle time 250 ns tWH(CNTR) CNTR0, CNTR1 input “H” pulse width 105 ns tWL(CNTR) CNTR0, CNTR1 input “L” pulse width 105 ns tWH(INT) INT0 −INT2 input “H” pulse width 80 ns tWL(INT) INT0 −INT2 input “L” pulse width 80 ns tC(SCLK) Serial I/O1, 2 clock input cycle time (3) 800 ns tWH(SCLK) Serial I/O1, 2 clock input “H” pulse width (3) 370 ns tWL(SCLK) Serial I/O1, 2 clock input “L” pulse width (3) 370 ns tsu(RXD-SCLK) Serial I/O1, 2 input setup time 220 ns th(SCLK-RXD) Serial I/O1, 2 input hold time 100 ns Table 31 Timing requirements (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted) Symbol Parameter Limits Unit Min. Typ. Max. tW(RESET) Reset input “L” pulse width 2 μs tC(XIN) Main clock input cycle time (XIN input) 2.0V ≤ VCC ≤ 4.0V 125 ns VCC < 2.0V 166 ns tWH(XIN) Main clock input “H” pulse width 2.0V ≤ VCC ≤ 4.0V 50 ns VCC < 2.0V 70 ns tWL(XIN) Main clock input “L” pulse width 2.0V ≤ VCC ≤ 4.0V 50 ns VCC < 2.0V 70 ns tC(CNTR) CNTR0, CNTR1 input cycle time 2.0V ≤ VCC ≤ 4.0V 1000/ VCC ns VCC < 2.0V 1000/(5 × VCC-8) ns tWH(CNTR) CNTR0, CNTR1 input “H” pulse width tc(CNTR)/2-20 ns tWL(CNTR) CNTR0, CNTR1 input “L” pulse width tc(CNTR)/2-20 ns tWH(INT) INT0 −INT2 input “H” pulse width 230 ns tWL(INT) INT0 −INT2 input “L” pulse width 230 ns tC(SCLK) Serial I/O1, 2 clock input cycle time (1) 2000 ns tWH(SCLK) Serial I/O1, 2 clock input “H” pulse width (1) 950 ns tWL(SCLK) Serial I/O1, 2 clock input “L” pulse width (1) 950 ns tsu(RXD-SCLK) Serial I/O1, 2 input setup time 400 ns th(SCLK-RXD) Serial I/O1, 2 input hold time 200 ns QzROM VERSION |
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