38D2 datasheet(103/136 Pages) RENESAS

103 / 136 page

Rev.3.02

Apr 10, 2008

Page 103 of 131

REJ03B0177-0302

38D2 Group

NOTE:

1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [001F16]) of UART control register is “0”.

NOTE:

1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [001F16]) of UART control register is “0”.

Fig 94. Circuit for measuring output switching characteristics

Table 32 Switching characteristics (1)

(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta =

−20 to 85°C, unless otherwise noted)

Symbol

Parameter

Limits

Unit

Min.

Typ

Max.

tWH(SCLK)

Serial I/O1, 2 clock output “H” pulse width

tc(SCLK)/2-30

tWL(SCLK)

Serial I/O1, 2 clock output “L” pulse width

tc(SCLK)/2-30

td(SCLK-TxD)

Serial I/O1, 2 output delay time (1)

140

tv(SCLK-TxD)

Serial I/O1, 2 output valid time (1)

−30

tr(SCLK)

Serial I/O1, 2 clock output rising time

tf(SCLK)

Serial I/O1, 2 clock output falling time

Table 33 Switching characteristics (2)

(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta =

−20 to 85°C, unless otherwise noted)

Symbol

Parameter

Limits

Unit

Min.

Typ

Max.

tWH(SCLK)

Serial I/O1, 2 clock output “H” pulse width

tc(SCLK)/2-80

tWL(SCLK)

Serial I/O1, 2 clock output “L” pulse width

tc(SCLK)/2-80

td(SCLK-TxD)

Serial I/O1, 2 output delay time (1)

350

tv(SCLK-TxD)

Serial I/O1, 2 output valid time (1)

-30

tr(SCLK)

Serial I/O1, 2 clock output rising time

tf(SCLK)

Serial I/O1, 2 clock output falling time

Measurement output pin

100pF

CMOS output

Measurement output pin

100pF

N-channel open-drain output (Note)

Note: When bit 4 of the UART control register

(address 001B16 [address 0FF116]) is “1.”

(N-channel open-drain output mode)

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