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HD64F36022 Datasheet(PDF) 116 Page - Renesas Technology Corp |
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HD64F36022 Datasheet(HTML) 116 Page - Renesas Technology Corp |
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116 / 384 page  Section 7 ROM Rev. 4.00 Sep. 23, 2005 Page 90 of 354 REJ09B0025-0400 Erase start Set EBR1 Enable WDT Wait 1 µs Wait 100 µs SWE bit ← 1 n ← 1 ESU bit ← 1 E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 10 10 µs Disable WDT Read verify data Increment address Verify data + all 1s ? Last address of block ? All erase block erased ? Set block start address as verify address H'FF dummy write to verify address Wait 20 µs Wait 2 µs EV bit ← 1 Wait 100 µs End of erasing Note: * The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading. SWE bit ← 0 Wait 4 µs EV bit ← 0 n ≤100 ? Wait 100 µs Erase failure SWE bit ← 0 Wait 4 µs EV bit ← 0 n ← n + 1 Yes No Yes Yes Yes Yes No No No * Figure 7.4 Erase/Erase-Verify Flowchart |
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