HD64F36022 datasheet(115/384 Pages) RENESAS

115 / 384 page

Section 7 ROM

Rev. 4.00 Sep. 23, 2005 Page 89 of 354

REJ09B0025-0400

5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two

bits are B'00. Verify data can be read in longwords from the address to which a dummy write

was performed.

6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-

verify sequence as before. The maximum number of repetitions of the erase/erase-verify

sequence is 100.

7.4.3

Interrupt Handling when Programming/Erasing Flash Memory

All interrupts, including the

NMI interrupt, are disabled while flash memory is being programmed

or erased, or while the boot program is executing, for the following three reasons:

1. Interrupt during programming/erasing may cause a violation of the programming or erasing

algorithm, with the result that normal operation cannot be assured.

2. If interrupt exception handling starts before the vector address is written or during

programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.

3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be

carried out.

HD64F36022 Datasheet(PDF) 115 Page - Renesas Technology Corp