HD64F36022 datasheet(114/384 Pages) RENESAS

114 / 384 page

Section 7 ROM

Rev. 4.00 Sep. 23, 2005 Page 88 of 354

REJ09B0025-0400

Table 7.4

Reprogram Data Computation Table

Program Data

Verify Data

Reprogram Data

Comments

Programming completed

Reprogram bit

—

Remains in erased state

Table 7.5

Additional-Program Data Computation Table

Reprogram Data

Verify Data

Additional-Program

Data

Comments

Additional-program bit

No additional programming

Table 7.6

Programming Time

(Number of Writes)

Programming

Time

In Additional

Programming

Comments

1 to 6

7 to 1,000

200

—

Note:

Time shown in

µs.

7.4.2

Erase/Erase-Verify

When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be

followed.

1. Prewriting (setting erase block data to all 0s) is not necessary.

2. Erasing is performed in block units. Make only a single-bit specification in the erase block

3. The time during which the E bit is set to 1 is the flash memory erase time.

4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An

overflow cycle of approximately 19.8 ms is allowed.

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