HD64F36022 datasheet(113/384 Pages) RENESAS

113 / 384 page

Section 7 ROM

Rev. 4.00 Sep. 23, 2005 Page 87 of 354

REJ09B0025-0400

The maximum number of repetitions of the program/program-verify sequence of the same bit

is 1,000.

START

End of programming

Note: *The RTS instruction must not be used during the following 1. and 2. periods.

1. A period between 128-byte data programming to flash memory and the P bit clearing

2. A period between dummy writing of H'FF to a verify address and verify data reading

Set SWE bit in FLMCR1

Write pulse application subroutine

Wait 1

µs

Apply Write Pulse

End Sub

Set PSU bit in FLMCR1

WDT enable

Disable WDT

Wait 50

µs

Set P bit in FLMCR1

Wait (Wait time=programming time)

Clear P bit in FLMCR1

Wait 5

µs

Clear PSU bit in FLMCR1

Wait 5

µs

n= 1

m= 0

Yes

Wait 4

µs

Wait 2

µs

Wait 2

µs

Apply Write pulse

Set PV bit in FLMCR1

Set block start address as

verify address

H'FF dummy write to verify address

Read verify data

Verify data =

write data?

Reprogram data computation

Additional-programming data computation

Clear PV bit in FLMCR1

Clear SWE bit in FLMCR1

m = 1

m= 0 ?

Increment address

Programming failure

Clear SWE bit in FLMCR1

Wait 100

µs

Yes

≤ 6?

Yes

≤ 6 ?

Wait 100

µs

≤ 1000 ?

← n + 1

Write 128-byte data in RAM reprogram

data area consecutively to flash memory

Store 128-byte program data in program

data area and reprogram data area

Apply Write Pulse

Sub-Routine-Call

128-byte

data verification completed?

Successively write 128-byte data from additional-

programming data area in RAM to flash memory

Figure 7.3 Program/Program-Verify Flowchart

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