HD64F36022 datasheet(260/384 Pages) RENESAS

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Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional)

Rev. 4.00 Sep. 23, 2005 Page 234 of 354

REJ09B0025-0400

15.3.2

Low-Voltage Detection Circuit

(1)

LVDR (Reset by Low Voltage Detect) Circuit

Figure 15.3 shows the timing of the LVDR function. The LVDR enters the module-standby state

after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait

for 50

µs (t

LVDON) until the reference voltage and the low-voltage-detection power supply have

stabilized by a software timer, etc., then set the LVDRE bit in LVDCR to 1. After that, the output

settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDRE bit

should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and LVDRE bits

must not be cleared to 0 simultaneously because incorrect operation may occur.

When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.6 V), the LVDR

clears the

LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state

remains in place until a power-on reset is generated. When the power-supply voltage rises above

the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock (

φ) cycles, and

then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in

LVDCR are not initialized.

Note that if the power supply voltage (Vcc) falls below V

LVDRmin = 1.0 V and then rises from that

point, the low-voltage detection reset may not occur.

If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.

LVDRES

VCC

Vreset

VSS

VLVDRmin

OVF

PSS-reset

signal

Internal reset

signal

131,072 cycles

PSS counter starts

Reset released

Figure 15.3 Operational Timing of LVDR Circuit

HD64F36022 Datasheet(PDF) 260 Page - Renesas Technology Corp

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