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HD64F36022 Datasheet(PDF) 261 Page - Renesas Technology Corp |
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HD64F36022 Datasheet(HTML) 261 Page - Renesas Technology Corp |
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261 / 384 page ![]() Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional) Rev. 4.00 Sep. 23, 2005 Page 235 of 354 REJ09B0025-0400 (2) LVDI (Interrupt by Low Voltage Detect) Circuit Figure 15.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 50 µs (t LVDON) until the reference voltage and the low-voltage-detection power supply have stabilized by a software timer, etc., then set the LVDDE and LVDUE bits in LVDCR to 1. After that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits because incorrect operation may occur. When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time, an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be saved in the external EEPROM, etc, and a transition must be made to standby mode or subsleep mode. Until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously generated. If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function is performed. LVDINT Vcc Vint (D) Vint (U) VSS LVDDF LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated LVDDE Vreset1 Figure 15.4 Operational Timing of LVDI Circuit |
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