SH7101 datasheet(370/560 Pages) RENESAS

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Section 11 A/D Converter

Rev.1.00 Sep. 18, 2008 Page 336 of 522

REJ09B0069-0100

Bit

Bit Name

Initial Value

R/W

Description

TRGE

R/W

Trigger Enable

Enables or disables triggering of A/D conversion by

ADTRG, an MTU trigger, or an MMT trigger.

0: A/D conversion triggering is disabled

1: A/D conversion triggering is enabled

CKS1

CKS0

R/W

Clock Select 0 and 1

Select the A/D conversion time.

00: P

φ/32

01: P

φ/16

10: P

φ/8

11: P

φ/4

When changing the A/D conversion time, first clear

the ADST bit in the A/D control registers (ADCRs) to

CKS[1,0] = b'11 can be set while P

φ ≤ 25 MHz.

ADST

R/W

A/D Start

Starts or stops A/D conversion. When this bit is set to

1, A/D conversion is started. When this bit is cleared

to 0, A/D conversion is stopped and the A/D converter

enters the idle state. In single or single-cycle scan

mode, this bit is automatically cleared to 0 when A/D

conversion ends on the selected single channel. In

continuous scan mode, A/D conversion is

continuously performed for the selected channels in

sequence until this bit is cleared by a software, reset,

or in software standby mode, hardware standby

mode, or module standby mode.

ADCS

R/W

A/D Continuous Scan

Selects either single-cycle scan or continuous scan in

scan mode. This bit is valid only when scan mode is

selected.

0: Single-cycle scan

1: Continuous scan

When changing the operating mode, first clear the

ADST bit in the A/D control registers (ADCRs) to 0.

2 to 0 —

All 1

Reserved

These bits are always read as 1. The write value

should always be 1.

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