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SH7101 Datasheet(PDF) 372 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 372 Page - Renesas Technology Corp |
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372 / 560 page ![]() Section 11 A/D Converter Rev.1.00 Sep. 18, 2008 Page 338 of 522 REJ09B0069-0100 Bit Bit Name Initial Value R/W Description 1 0 TRG0S1 TRG0S0 0 0 R/W R/W AD Trigger 0 Select 1 and 0 Enable the start of A/D conversion by A/D0 with a trigger signal. 00: A/D conversion start by external trigger pin ( ADTRG) or MTU trigger is enabled 01: A/D conversion start by external trigger pin ( ADTRG) is enabled 10: A/D conversion start by MTU trigger is enabled 11: A/D conversion start by MMT trigger is enabled When changing the operating mode, first clear the TRGE and ADST bits in the A/D control registers (ADCRs) to 0. 11.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. There are two kinds of scan mode: continuous mode and single-cycle mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the ADST bit to 0 in ADCR. The ADST bit can be set at the same time when the operating mode is changed. 11.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. The operations are as follows. 1. A/D conversion is started when the ADST bit in ADCR is set to 1, according to software, MTU, MMT, or external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state. |
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