SH7101 datasheet(376/560 Pages) RENESAS

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Section 11 A/D Converter

Rev.1.00 Sep. 18, 2008 Page 342 of 522

REJ09B0069-0100

11.4.4

Input Sampling and A/D Conversion Time

The A/D converter has an on-chip sample-and-hold circuit for each module. The A/D converter

samples the analog input when the A/D conversion start delay time (t

D) has passed after the ADST

bit in ADCR is set to 1, then starts conversion. Figure 11.3 shows the A/D conversion timing.

Table 11.3 shows the A/D conversion time.

As indicated in figure 11.3, the A/D conversion time (t

CONV) includes tD and the input sampling time

SPL).

The length of t

D varies depending on the timing of the write access to ADCR. The total

conversion time therefore varies within the ranges indicated in table 11.3.

In scan mode, the values given in table 11.3 apply to the first conversion time. The values given

in table 11.4 apply to the second and subsequent conversions.

A/D converter

A/D conversion

A/D conversion start

delay time(tD)

A/D conversion time (tCONV)

Analog input

sampling time(tSPL)

ADST write timing

End of A/D conversion

ADF

Address

Write cycle

A/D synchronization time

(3 states)

(Up to

59 states)

Internal write

signal

Analog input

sampling

signal

Idle state

Sample-and-hold

Figure 11.3 A/D Conversion Timing

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