SH7101 datasheet(387/560 Pages) RENESAS

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Section 12 Compare Match Timer (CMT)

Rev.1.00 Sep. 18, 2008 Page 353 of 522

REJ09B0069-0100

12.2.2

Compare Match Timer Control/Status Registers_0 and 1 (CMCSR_0, CMCSR_1)

CMCSR is a 16-bit register that indicates the occurrence of compare matches, enables or disables

interrupts, and sets the clock used for incrementation.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CMF

R/(W)* Compare Match Flag

Indicates whether or not the CMCNT and CMCOR values

have matched.

0: CMCNT and CMCOR values have not matched

[Clearing condition]

• Write 0 to CMF after reading 1 from it

1: CMCNT and CMCOR values have matched

CMIE

R/W

Compare Match Interrupt Enable

Selects whether to enable or disable a compare match

interrupt (CMI) when the CMCNT and CMCOR values

have matched (CMF = 1).

0: Compare match interrupt (CMI) disabled

1: Compare match interrupt (CMI) enabled

5 to 2

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CKS1

CKS0

R/W

Select the clock input to CMCNT among the four internal

clocks obtained by dividing the peripheral clock (P

φ).

When the STR bit in CMSTR is set to 1, CMCNT begins

incrementing with the clock selected by the CKS1 and

CKS0 bits.

00: P

φ/8

01: P

φ/32

10: P

φ/128

11: P

φ/512

Note:

Only 0 can be written for flag clearing.

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