SH7101 datasheet(389/560 Pages) RENESAS

389 / 560 page

Section 12 Compare Match Timer (CMT)

Rev.1.00 Sep. 18, 2008 Page 355 of 522

REJ09B0069-0100

12.3.2

CMCNT Count Timing

One of four internal clocks (P

φ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral

clock (P

φ) can be selected by the CKS1 and CKS0 bits in CMCSR. Figure 12.3 shows the timing.

Internal

clock

CMCNT

input clock

CMCNT

N-1

N+1

Figure 12.3 Count Timing

12.4

Interrupts

12.4.1

Interrupt Sources

The CMT has a compare match interrupt for each channel, with independent vector addresses

allocated to each of them. The corresponding interrupt request is output when the interrupt request

flag (CMF) is set to 1 and interrupt enable bit (CMIE) has also been set to 1.

When activating CPU interrupts by an interrupt request, the priority between the channels can be

changed by means of interrupt controller settings. See section 6, Interrupt Controller (INTC), for

details.

12.4.2

Compare Match Flag Set Timing

The CMF bit in CMCSR is set to 1 by the compare match signal generated when CMCOR and

CMCNT match. The compare match signal is generated upon the final state of the match (timing

at which the CMCNT matching count value is updated). Consequently, after CMCOR and

CMCNT match, a compare match signal will not be generated until a CMCNT counter input clock

occurs. Figure 12.4 shows the CMF bit set timing.

SH7101 Datasheet(PDF) 389 Page - Renesas Technology Corp