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SH7101 Datasheet(PDF) 393 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  560 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 393 Page - Renesas Technology Corp

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Section 12 Compare Match Timer (CMT)
Rev.1.00 Sep. 18, 2008 Page 359 of 522
REJ09B0069-0100
12.5.3
Contention between CMCNT Byte Write and Incrementation
If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has
priority, so no increment of the write data results on the side on which the write was performed.
The byte data on the side on which writing was not performed is also not incremented, so the
contents are those before the write.
Figure 12.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write
cycle.
P
φ
T1
T2
Address
CMCNTH
Internal write
signal
CMCNTH
NM
CMCNTL
XX
CMCNTH write data
CMCNT input
clock
CMCNT write cycle
Figure 12.8 CMCNT Byte Write and Increment Contention



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