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SH7101 Datasheet(PDF) 416 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 416 Page - Renesas Technology Corp |
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416 / 560 page  Section 13 Motor Management Timer (MMT) Rev.1.00 Sep. 18, 2008 Page 382 of 522 REJ09B0069-0100 13.6.2 Interrupt Signal Timing (1) Timing of TGF Flag Setting by Compare Match Figure 13.12 shows the timing of setting of the TGF flag in the timer status register (TSR) on a compare match between TCNT and TPDR, and the timing of the TGI interrupt request signal. The timing is the same for a compare match between TCNT and 2Td. N TPDR N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 TCNT Compare match signal TGF flag TGI interrupt P φ Figure 13.12 TGI Interrupt Timing (2) Status Flag Clearing Timing A status flag is cleared when the CPU reads 1 from the flag, then 0 is written to it. Figure 13.13 shows the timing of status flag clearing by the CPU. TSR address P Address Interrupt request signal Status flag Write signal T1 T2 TSR write cycle Figure 13.13 Timing of Status Flag Clearing by CPU |
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