SH7101 datasheet(413/560 Pages) RENESAS

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Section 13 Motor Management Timer (MMT)

Rev.1.00 Sep. 18, 2008 Page 379 of 522

REJ09B0069-0100

• Halting MMT output when oscillation stops

The six-phase PWM output pins are placed in the high-impedance state automatically when

stoppage of the clock input is detected. However, pin states are not guaranteed when the clock

is restarted.

13.5

Interrupt Sources

When the TGFM (TGFN) flag is set to 1 in the timer status register (TSR) by a compare match

between TCNT and TPDR (2Td), and if the TGIEM (TGIEN) bit setting in the timer control

TGF flag to 0.

Table 13.4

MMT Interrupt Sources

Name

Interrupt Source

Interrupt Flag

TGIMN

Compare match between TCNT and TPDR

TGFM

TGINN

Compare match between TCNT and 2Td

TGFN

The on-chip A/D converter can be activated when TCNT matches TPDR or 2Td. When the TGF

flag in the timer status register (TSR) is set to 1 as a result of either match, a request to start A/D

conversion is sent to the A/D converter. If the conversion start trigger of the MMT is selected in

the A/D converter at that time, A/D conversion starts.

13.6

Operation Timing

13.6.1

Input/Output Timing

(1) TCNT and TDCNT Count Timing

Figure 13.8 shows the TCNT and TDCNT count timing.

N – 3

N – 2

N – 1

N + 1 N + 2 N + 3

N + 4

TCNT,

TDCNT

Figure 13.8 Count Timing

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