SH7101 datasheet(411/560 Pages) RENESAS

411 / 560 page

Section 13 Motor Management Timer (MMT)

Rev.1.00 Sep. 18, 2008 Page 377 of 522

REJ09B0069-0100

is performed when a value greater than the TPDR value is set as the buffer register (TBRU to

TBRW) value. The waveform in this case has positive phase in the 100% off state.

(11) External Counter Clear Function

In the operating modes, the TCNT counter can be cleared from an external source. When using the

counter clearing function, the port A I/O register L (PAIORL) should be used to set the PCIO pin

as an input.

On the falling edge of the PCIO pin (when set to input), the TCNT counter is reset to 2Td (the

initial setting). It then counts up until it reaches the value in TPDR, then starts counting down.

When the count returns to 2Td, TCNT starts counting up again, and this sequence is repeated.

Figure 13.6 shows the example for counter clearing.

TCNT

TPDR

2Td

H'0000

PCIO pin

(counter clear

input)

Figure 13.6 Example of TCNT Counter Clearing

(12) Toggle Output Synchronized with PWM Cycle

In the operating modes, output can be toggled synchronously with the PWM carrier cycle. When

outputting the PWM cycle, the pin function controller (PFC) should be used to set the PCIO pin as

an output (when set to output). An example of the toggle output waveform is shown in figure 13.7.

PWM cycle output is toggled according to the TCNT count direction. The toggle output pin is

PCIO (when set to output). The PCIO pin outputs 1 when TCNT is counting up, and 0 when

counting down.

SH7101 Datasheet(PDF) 411 Page - Renesas Technology Corp