SH7101 datasheet(407/560 Pages) RENESAS

407 / 560 page

Section 13 Motor Management Timer (MMT)

Rev.1.00 Sep. 18, 2008 Page 373 of 522

REJ09B0069-0100

Compared during

up-count

Compared during

down-count

Compared during

up-count

Compared during

down-count

Up-count

compare

match

down-count

Down-count

compare

match

up-count

Constantly

compared

(TBR + 2Td)

(TBR + Td)

(TBR)

TGRUU

TGRVU

TGRWU

TGRU

TGRV

TGRW

TGRUD

TGRVD

TGRWD

TPDR

TCNT

(1/2 period + 2Td)

TDDR

(Td)

TPBR

(1/2 period)

TDDR

TDCNT

(Td)

TBRU

TBRV

TBRW

(TBR)

(2Td)

Up-count

compare match

halt

TCNT

Figure 13.4 Examples of Counter and Register Operations

(3) Initial Settings

In the operating modes, there are five registers that require initialization.

Make the following register settings before setting the operating mode with bits MD1 and MD0 in

the timer mode register (TMDR).

Set the timer period buffer register (TPBR) to 1/2 the PWM carrier period, set dead time Td in the

timer dead time data register (TDDR) (when outputting an ideal waveform, Td = H'0000), and set

{TPBR value + 2Td} in the timer period data register (TPDR).

Set {PWM duty initial value – Td} in the free write operation addresses for TBRU to TBRW.

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