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SH7101 Datasheet(PDF) 408 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  560 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 408 Page - Renesas Technology Corp

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Section 13 Motor Management Timer (MMT)
Rev.1.00 Sep. 18, 2008 Page 374 of 522
REJ09B0069-0100
The values of TBRU to TBRW should always be set in the range H'0000 to H'FFFF – 2Td, and the
value of TPBR should always be set in the range H'0000 to H'FFFF – 4Td.
(4) PWM Output Active Level Setting
In the operating modes, the active level of PWM pulses is set with bits OLSN and OLSP in the
timer mode register (TMDR).
The output level can be set for the three positive phases and the three negative phases of six-phase
output. The operating mode must be exited before setting or changing the output level.
(5) Dead Time Setting
In the operating modes, PWM pulses are output with a non-overlap relationship between the
positive and negative phases. This non-overlap time is known as the dead time. The non-overlap
time is set in the timer dead time data register (TDDR). The dead time generation waveform is
generated by comparing the value set in TDDR with the timer dead time counters (TDCNT) for
each phase. The operating mode must be exited before changing the contents of TDDR.
(6) PWM Period Setting
In the operating modes, 1/2 the PWM pulse period is set in TPBR. The TPBR value should always
be set in the range H'0000 to H'FFFF – 4Td. The value set in TPBR is transferred to TPDR at the
timing selected with bits MD1 and MD0 in the timer mode register (TMDR). After the transfer,
the value in TPDR is {TPBR value + 2Td}.
The new PWM period is effective from the next period when data is updated at the TCNT counter
peak, and from the same period when data is updated at the trough.
(7) Register Updating
In the operating modes, buffer registers are used to update compare register data. Update data can
be written to a buffer register at all times. The buffer register value is transferred to the compare
register at the timing set by bits MD1 and MD0 in the timer mode register (TMDR) (except in the
case of a write to the free operation address for TBRU to TBRW, in which case the value is
transferred to the corresponding compare register immediately).
(8) Initial Output in Operating Modes
The initial output in the operating modes is determined by the initial values of TBRU to TBRW.
Table 13.2 shows the relationship between the initial value of TBRU to TBRW and the initial
output.



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