SH7101 datasheet(405/560 Pages) RENESAS

405 / 560 page

Section 13 Motor Management Timer (MMT)

Rev.1.00 Sep. 18, 2008 Page 371 of 522

REJ09B0069-0100

(1) Count Operation

Set 2Td (Td: value set in TDDR) as the initial value of the TCNT counter when the CST bit in

TCNR is cleared to 0.

When the CST bit is set to 1, TCNT counts up to {the value set in TPBR + 2Td}, and then starts

counting down. When TCNT reaches 2Td, it starts counting up again, and continues in this way.

TCNT is constantly compared with TGRU, TGRV, and TGRW. In addition, it is compared with

TGRUU, TGRVU, TGRWU, and TPDR when counting up, and with TGRUD, TGRVD,

TGRWD, and 2Td when counting down.

TDCNT0 to TDCNT5 are read-only counters. It is not necessary to set their initial values.

TDCNT0, TDCNT2, and TDCNT4 start counting up at the falling edge of a positive phase

compare match output when TCNT is counting down. When they become equal to TDDR they are

cleared to 0 and halt.

TDCNT1, TDCNT3, and TDCNT5 start counting up at the falling edge of a negative phase

compare match output when TCNT is counting up. When they match TDDR they are cleared to 0

and halt.

TDCNT0 to TDCNT5 are compared with TDDR only while a count operation is in progress. No

count operation is performed when the TDDR value is 0.

Figure 13.3 shows an example of the TCNT count operation.

TCNT

H'FFFF

H'0000

TPDR

TGRUU

TGRU

TGRUD

2Td

1/2 period

(TPBR)

Figure 13.3 Example of TCNT Count Operation

SH7101 Datasheet(PDF) 405 Page - Renesas Technology Corp