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SH7101 Datasheet(PDF) 417 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  560 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 417 Page - Renesas Technology Corp

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Section 13 Motor Management Timer (MMT)
Rev.1.00 Sep. 18, 2008 Page 383 of 522
REJ09B0069-0100
13.7
Usage Notes
13.7.1
Module Standby Mode Setting
MMT operation can be disabled or enabled using the module standby control register. The initial
setting is for MMT operation to be halted. Register access is enabled by clearing module standby
mode. For details, refer to section 18, Power-Down Modes.
13.7.2
Notes on MMT Operation
Note that the kinds of operation and contention described below occur during MMT operation.
(1) Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a buffer register (TBRU to TBRW, or TPBR) write
cycle, data is transferred from the buffer register to the compare register (TGR or TPDR) by a
buffer operation. The data transferred is the buffer register write data.
Figure 13.14 shows the timing in this case.
Buffer register write data
NM
M
P
φ
Address
Compare match
signal
Interrupt request
signal
Buffer register
Compare register
Write signal
Buffer register
address
T1
T2
Buffer register
write cycle
Figure 13.14 Contention between Buffer Register Write and Compare Match



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