SH7101 datasheet(422/560 Pages) RENESAS

422 / 560 page

Section 13 Motor Management Timer (MMT)

Rev.1.00 Sep. 18, 2008 Page 388 of 522

REJ09B0069-0100

(1) Input Level Control/Status Register 2 (ICSR2)

ICSR2 is a 16-bit readable/writable register that selects the input mode for pins

POE4 to POE6,

controls enabling or disabling of interrupts, and holds status information.

Bit

Bit Name

Initial

Value

R/W

Description

⎯

Reserved

This bit is always read as 0. The write value should

always be 0.

POE6F

R/(W)*

POE6 Flag

Indicates that a high impedance request has been input

to the

POE6 pin.

[Clearing condition]

• When 0 is written to POE6F after reading POE6F =

[Setting condition]

• When the input set by bits 4 and 5 in ICSR2 occurs

at the

POE6 pin

POE5F

R/(W)*

POE5 Flag

Indicates that a high impedance request has been input

to the

POE5 pin.

[Clearing condition]

• When 0 is written to POE5F after reading POE5F =

[Setting condition]

• When the input set by bits 2 and 3 in ICSR2 occurs

at the

POE5 pin

POE4F

R/(W)*

POE4 Flag

Indicates that a high impedance request has been input

to the

POE4 pin.

[Clearing condition]

• When 0 is written to POE4F after reading POE4F =

[Setting condition]

• When the input set by bits 0 and 1 in ICSR2 occurs

at the

POE4 pin

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