SH7101 datasheet(423/560 Pages) RENESAS

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Section 13 Motor Management Timer (MMT)

Rev.1.00 Sep. 18, 2008 Page 389 of 522

REJ09B0069-0100

Bit

Bit Name

Initial

Value

R/W

Description

11 to 9

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

PIE

R/W

Port Interrupt Enable

Enables or disables an interrupt request when 1 is set in

any of bits POE4F to POE6F in ICSR2.

0: Interrupt request disabled

1: Interrupt request enabled

7, 6

⎯

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

POE6M1

POE6M0

R/W

POE6 Mode 1 and 0

Select the input mode of the

POE6 pin.

00: Request accepted at falling edge of

POE6 input

01:

POE6 input is sampled for low level 16 times every

φ/8 clock, and request is accepted when all

samples are low level

10:

POE6 input is sampled for low level 16 times every

φ/16 clock, and request is accepted when all

samples are low level

11:

POE6 input is sampled for low level 16 times every

φ/128 clock, and request is accepted when all

samples are low level

POE5M1

POE5M0

R/W

POE5 Mode 1 and 0

Select the input mode of the

POE5 pin.

00: Request accepted at falling edge of

POE5 input

01:

POE5 input is sampled for low level 16 times every

φ/8 clock, and request is accepted when all

samples are low level

10:

POE5 input is sampled for low level 16 times every

φ/16 clock, and request is accepted when all

samples are low level

11:

POE5 input is sampled for low level 16 times every

φ/128 clock, and request is accepted when all

samples are low level

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