SH7101 datasheet(424/560 Pages) RENESAS

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Section 13 Motor Management Timer (MMT)

Rev.1.00 Sep. 18, 2008 Page 390 of 522

REJ09B0069-0100

Bit

Bit Name

Initial

Value

R/W

Description

POE4M1

POE4M0

R/W

POE4 Mode 1 and 0

Select the input mode of the

POE4 pin.

00: Request accepted at falling edge of

POE4 input

01:

POE4 input is sampled for low level 16 times every

φ/8 clock, and request is accepted when all

samples are low level

10:

POE4 input is sampled for low level 16 times every

φ/16 clock, and request is accepted when all

samples are low level

11:

POE4 input is sampled for low level 16 times every

φ/128 clock, and request is accepted when all

samples are low level

Note:

Only 0 can be written to clear the flag.

13.8.4

Operation

(1) Input Level Detection

When the input condition set in ICSR2 occurs on any one of the

POE pins, the MMT output pins

enter the high-impedance state.

• Pins placed in the high-impedance state (the MMT’s output pins)

The six pins PWOB, PWOA, PVOB, PVOA, PUOB, and PUOA in the motor management

timer (MMT) are placed in the high-impedance state.

Note:

These pins are in the high-impedance state only when each pin is used as the general

input/output function or MMT output pin.

(a) Falling Edge Detection

When a transition from high- to low-level input occurs on a

POE pin

(b) Low Level Detection

Figure 13.18 shows the low level detection operation. Low level sampling is performed 16 times

in succession using the sampling clock set in ICSR2. The input is not accepted if a high level is

detected even once among these samples.

The timing of entry of the MMT's output pins into the high-impedance state from the sampling

clock is the same for falling edge detection and low level detection.

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