SH7101 datasheet(501/560 Pages) RENESAS

501 / 560 page

Section 19 List of Registers

Rev.1.00 Sep. 18, 2008 Page 467 of 522

REJ09B0069-0100

Abbre-

viation

Bits Address

Module

Access

Size

Access

States

—

H'FFFF83A4 to

H'FFFF83A5

—

Port D I/O register L

PDIORL

H'FFFF83A6

PFC

8, 16

—

H'FFFF83A8 to

H'FFFF83AB

—

Port D control register L1

PDCRL1

H'FFFF83AC

PFC

8, 16, 32

Port D control register L2

PDCRL2

H'FFFF83AE

8, 16

Port E data register L

PEDRL

H'FFFF83B0

I/O

8, 16, 32

Port F data register

PFDR

H'FFFF83B2

8, 16

Port E I/O register L

PEIORL

H'FFFF83B4

PFC

8, 16, 32

Port E I/O register H

PEIORH

H'FFFF83B6

8, 16

Port E control register L1

PECRL1

H'FFFF83B8

8, 16, 32

Port E control register L2

PECRL2

H'FFFF83BA

8, 16

Port E control register H

PECRH

H'FFFF83BC

8, 16, 32

Port E data register H

PEDRH

H'FFFF83BE

I/O

8, 16

Input control/status register 1

ICSR1

H'FFFF83C0

MTU

8, 16, 32

Output control/status register

OCSR

H'FFFF83C2

8, 16

Input control/status register 2

ICSR2

H'FFFF83C4

MMT

8, 16

In P

φ cycles

B: 2

W: 2

L: 4

—

H'FFFF83C6 to

H'FFFF83CC

—

Port G data register

PGDR

H'FFFF83CD

I/O

φ cycles

B: 2

W: 2

L: 4

—

H'FFFF83CE to

H'FFFF83CF

—

Compare match timer start

CMSTR

H'FFFF83D0

CMT

8, 16, 32

Compare match timer

control/status register_0

CMCSR_0

H'FFFF83D2

8, 16

In P

φ cycles

B: 2

W: 2

L: 4

Compare match timer counter_0

CMCNT_0

H'FFFF83D4

8, 16, 32

Compare match timer constant

register_0

CMCOR_0

H'FFFF83D6

8, 16

Compare match timer

control/status register_1

CMCSR_1

H'FFFF83D8

8, 16, 32

Compare match timer counter_1

CMCNT_1

H'FFFF83DA

8, 16

Compare match timer constant

register_1

CMCOR_1

H'FFFF83DC

8, 16

—

H'FFFF83DE

—

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