SH7101 datasheet(503/560 Pages) RENESAS

503 / 560 page

Section 19 List of Registers

Rev.1.00 Sep. 18, 2008 Page 469 of 522

REJ09B0069-0100

Abbre-

viation

Bits Address

Module

Access

Size

Access

States

Timer control/status register

TCSR

H'FFFF8610

2/16*1

Timer counter

TCNT*

H'FFFF8610

Timer counter

TCNT*

H'FFFF8611

φ cycles

B: 3

W: 3

Reset control/status register

RSTCSR*

H'FFFF8612

Reset control/status register

RSTCSR*

H'FFFF8613

WDT

*1: Write

cycle

*2: Read

cycle

Standby control register

SBYCR

H'FFFF8614

Power-

down

modes

φ cycles

B: 3

—

H'FFFF8615 to

H'FFFF8617

—

System control register

SYSCR

H'FFFF8618

Power-

down

modes

—

H'FFFF8619 to

H'FFFF861B

—

Module standby control register 1 MSTCR1

H'FFFF861C

8, 16, 32

Module standby control register 2 MSTCR2

H'FFFF861E

8, 16

In P

φ cycles

B: 3

W: 3

L: 6

Bus control register 1

BCR1

H'FFFF8620

BSC

8, 16, 32

Bus control register 2

BCR2

H'FFFF8622

8, 16

Wait control register 1

WCR1

H'FFFF8624

8, 16

—

H'FFFF8626

—

φ cycles

B: 3

W: 3

L: 6

—

H'FFFF8628 to

H'FFFF864F

—

H'FFFF8650 to

H'FFFF87F3

—

A/D trigger select register

ADTSR

H'FFFF87F4

A/D

—

H'FFFF87F5 to

H'FFFF89FF

—

In P

φ cycles

B: 3

Timer mode register

MMT_TMDR

H'FFFF8A00

MMT

—

H'FFFF8A01

—

Timer control register

TCNR

H'FFFF8A02

—

H'FFFF8A03

—

Timer status register

MMT_TSR

H'FFFF8A04

—

H'FFFF8A05

—

In P

φ cycles

B: 2

W: 2

L: 4

Timer counter

MMT_TCNT

H'FFFF8A06

Timer period data register

TPDR

H'FFFF8A08

16, 32

Timer period buffer register

TPBR

H'FFFF8A0A

Timer dead time data register

MMT_TDDR

H'FFFF8A0C

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