SH7101 datasheet(137/560 Pages) RENESAS

137 / 560 page

Section 7 Bus State Controller (BSC)

Rev.1.00 Sep. 18, 2008 Page 103 of 522

REJ09B0069-0100

Bit

Bit Name

Initial

Value

R/W

Description

⎯

Reserved

This bit is always read as 0. The write value should

always be 0.

MMTRWE

R/W

MMT Read/Write Enable

This bit enables MMT control register access. For

details, refer to section 13, Motor Management Timer

(MMT).

0: MMT control register access is disabled

1: MMT control register access is enabled

MTURWE

R/W

MTU Read/Write Enable

This bit enables MTU control register access. For

details, refer to section 8, Multifunction Timer Pulse

Unit (MTU).

0: MTU control register access is disabled

1: MTU control register access is enabled

12 to 4

⎯

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

3 to 1

⎯

All 1

Reserved

These bits are always read as 1. The write value

should always be 1.

A0SZ

R/W

CS0 Space Size Specification

Specifies the CS0 space bus size when A0LG is 0.

In on-chip ROM enabled mode, 0 should be written to

this bit to specify a bus size of 8 bits before the CS0

space is accessed.

Note:

In on-chip ROM disabled mode, the CS0

space bus size is specified by the mode pin.

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