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SH7101 Datasheet(PDF) 140 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  560 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 140 Page - Renesas Technology Corp

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Section 7 Bus State Controller (BSC)
Rev.1.00 Sep. 18, 2008 Page 106 of 522
REJ09B0069-0100
7.6
Accessing External Space
A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct
connections.
7.6.1
Basic Timing
External access bus cycles are performed in 2 states. Figure 7.3 shows the basic timing of external
space access.
Write
Data
Data
Address
CK
Read
T1
T2
Figure 7.3 Basic Timing of External Space Access
During a read, irrespective of operand size, all bits (8 bits in this LSI) in the data bus width for the
access space (address) accessed by
RD signal are fetched by the LSI.
During a write, the
WRL (bits 7 to 0) signal indicates the byte location to be written.



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