SH7101 datasheet(152/560 Pages) RENESAS

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Section 8 Multifunction Timer Pulse Unit (MTU)

Rev.1.00 Sep. 18, 2008 Page 118 of 522

REJ09B0069-0100

Internal data bus

A/D converter conversion

start signal

Legend:

TSTR:

TSYR:

TCR:

TMDR:

TIOR (H, L):

Timer start register

Timer synchro register

Timer control register

Timer mode register

Timer I/O control registers (H, L)

TIER:

TSR:

TCNT:

TGR (A, B, C, D):

Timer interrupt enable register

Timer status register

Timer counter

Timer general registers (A, B, C, D)

Interrupt request signals

Channel 3:

Channel 4:

TGI3A

TGI3B

TGI3C

TGI3D

TCI3V

TGI4A

TGI4B

TCI4C

TCI4D

TGI4V

Interrupt request signals

Channel 0:

Channel 1:

Channel 2:

TGI0A

TGI0B

TGI0C

TGI0D

TCI0V

TGI1A

TGI1B

TCI1V

TCI1U

TGI2A

TGI2B

TCI2V

TCI2U

TIOC0A

TIOC0B

TIOC0C

TIOC0D

TIOC1A

TIOC1B

TIOC2A

TIOC2B

Input/output pins

Channel 0:

Channel 1:

Channel 2:

φ/1

φ/4

φ/16

φ/64

φ/256

φ/1024

TCLKA

TCLKB

TCLKC

TCLKD

Clock input

Internal clock:

External clock:

TIOC3A

TIOC3B

TIOC3C

TIOC3D

TIOC4A

TIOC4B

TIOC4C

TIOC4D

Input/output pins

Channel 3:

Channel 4:

Figure 8.1 Block Diagram of TPU

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