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SH7101 Datasheet(PDF) 162 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  560 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 162 Page - Renesas Technology Corp

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Section 8 Multifunction Timer Pulse Unit (MTU)
Rev.1.00 Sep. 18, 2008 Page 128 of 522
REJ09B0069-0100
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Bit
Bit Name
Initial value
R/W
Description
7
6
5
4
IOB3
IOB2
IOB1
IOB0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control B3 to B0
Specify the function of TGRB.
See the following tables.
TIORH_0: Table 8.10
TIOR_1:
Table 8.14
TIOR_2:
Table 8.16
TIORH_3: Table 8.18
TIORH_4: Table 8.22
3
2
1
0
IOA3
IOA2
IOA1
IOA0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control A3 to A0
Specify the function of TGRA.
See the following tables.
TIORH_0: Table 8.11
TIOR_1:
Table 8.15
TIOR_2:
Table 8.17
TIORH_3: Table 8.19
TIORH_4: Table 8.23
TIORL_0, TIORL_3, TIORL_4
Bit
Bit Name
Initial value
R/W
Description
7
6
5
4
IOD3
IOD2
IOD1
IOD0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control D3 to D0
Specify the function of TGRD.
When the TGRD is used as a buffer register of the
TGRB, this setting is invalid and input capture/output
compare is not generated.
See the following tables.
TIORL_0: Table 8.12
TIORL_3: Table 8.20
TIORL_4: Table 8.24
3
2
1
0
IOC3
IOC2
IOC1
IOC0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control C3 to C0
Specify the function of TGRC.
When the TGRC is used as a buffer register of the
TGRA, this setting is invalid and input capture/output
compare is not generated.
See the following tables.
TIORL_0: Table 8.13
TIORL_3: Table 8.21
TIORL_4: Table 8.25



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